verilogHDL分频器(奇数分频和偶数分频)
余年寄山水
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2021年01月24日 17:13
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module clk_div(
//-----------input-----------
iCLK,
div,
//-----------output----------
oCLK
);
//-----------input-----------
parameter
WIDE=14;
input
//-----------output-----------
output
oCLK;
wire
oCLK_odd;
iCLK;
input[WIDE-1:0]div;
wire
oCLK_even;
assign oCLK=div[0]?oCLK_odd:oCLK_even;
div_odd DUTo (.iCLK(iCLK),.oCLK(oCLK_odd),.div(div));
div_even DUTe (.iCLK(iCLK),.oCLK(oCLK_even),.div(div));
endmodule
// odd
module div_odd(
//--------input--------
iCLK,
div,
//--------output--------
oCLK
);
//--------input--------
parameter
input
WIDE=14;
iCLK;
input[WIDE-1:0]div;
//--------output--------
output
oCLK;
reg
outCLK;
/*
===========================
solve 1
===========================
reg
cout;
reg[WIDE-1:0] cnt;
initial
cnt=0;
wire
reg
initial
always @(posedge cout)
cc<=~cc;
inCLK;
cc;
cc=0;
assign inCLK = iCLK^cc;
always @(posedge inCLK)
begin
if(cnt<(div[WIDE-1:1]))
begin
cnt<=cnt+1;
cout<=1'b0;
end
else
begin
end
cnt<=0;
cout<=1'b1;
end
always @(negedge iCLK)
outCLK <= cout;
assign oCLK=cc;
*/
//========================
//solve 2
//========================
reg[WIDE-1:0] cnt_a;
initial
cnt_a=0;
reg[WIDE-1:0] cnt_b;
initial
cnt_b=0;
reg
cout_a;
reg
cout_b;
always @(negedge iCLK)
begin
end
else if(cnt_a<=(div[WIDE-1:1]))
begin
end
begin
cout_a=1'b0;
cnt_a=cnt_a+1;
cnt_a=cnt_a+1;
cout_a=1'b1;
else if(cnt_a>(div[WIDE-1:1])&&cnt_a<(div[WIDE-1:0]-1))
end
else
begin
cnt_a=0;
end
always @(posedge iCLK)
begin
end
if(cnt_b<=(div[WIDE-1:1]))
begin
cnt_b=cnt_b+1;
cout_b=1'b1;
end
else if(cnt_b>(div[WIDE-1:1])&&cnt_b<(div[WIDE-1:0]-1))
begin
cout_b=1'b0;
cnt_b=cnt_b+1;
end
else
begin
cnt_b=0;
end
assign oCLK = cout_a&cout_b;
endmodule